Typically, a computer system contains a processor, a bus, and other peripheral devices. The processor is responsible for executing instructions using the data in the computer system. The bus is used by the microprocessor and the peripheral devices for transferring information between one another. The information on the bus usually includes data, address and control signals. The peripheral devices comprise storage devices, input/output I/O devices, etc. Generally, all operations being performed in the computer system occur at the same frequency.
The microprocessor has a core for processing the data. Since generally all operations performed by the computer system occur at the same frequency, the logic operations performed by the core are at the same frequency as the transfer of data, address and control signals on the computer system bus.
Some logic operations performed by the core, such as arithmetic operations, require multiple cycles to complete. During completion of these multiple cycle operations, the bus remains idle. It is desirable to have the core operate at a faster speed than the bus, so that operations are performed more quickly. In this manner, the bus will be used more frequently, such that bus idle states will be reduced and operations performed more quickly.
When additional features are integrated in a microprocessor, its use must often require changes to the computer system to accommodate the new features. These changes could take the form of modifications to the circuit board, including adding extra circuitry. Changes which require modifications to the bus architecture including the bus width are generally expensive. Ideally, new features and faster processing should be added without changing, for example, the mother board of a computer system. It is thus advantageous to modify microprocessors by incorporating new features in such a way as to reduce or dispense with changes to the remainder of the computer system.
The present invention provides a microprocessor design which can have its core operate at a multiple (e.g., 2.times., 3.times., etc.) of the bus frequency. Thus, the present invention provides a microprocessor with a core that operates at multiple frequencies of the computer system bus transparently, such that the computer system does not know the core is operating faster and, thus, does not have to be changed to accommodate the microprocessor of the present invention. In this manner, the microprocessor of the present invention allows an upgrade to performance without having to redesign the personal computer board within the system.